1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a contact pad of a semiconductor device.
2. Description of the Related Art
As the density of a DRAM device is increased, the pattern line widths of various elements of the DRAM device are narrowed. Consequently, the aspect ratio becomes larger, and this larger aspect ratio makes it more difficult to form a contact that passes through the insulating layer to the semiconductor substrate. In order to solve this problem, contact pads are utilized, and a conventional process for forming a contact pad is described immediately below.
First, a gate electrode is formed on a semiconductor substrates and the upper surface and the side walls of the gate electrode are covered by a nitride layer. An impurity is implanted into the semiconductor substrate at the both sides of the gate electrode, thereby forming a source/drain region. Then a silicon nitride (SiN) layer is formed on the entire surface of the semiconductor substrate. The SiN layer prevents a device isolating region from being etched during a subsequent etching of an insulating layer in preparation for forming a contact pad. An inter-layer insulating layer is then formed on the SiN layer. Then a photoresist (PR) pattern is used as a mask to etch the inter-layer insulating layer to form an opening which exposes the source/drain region between the gates. The PR pattern is removed and a polysilicon layer is formed on the inter-layer insulating layer to fill the opening. The polysilicon layer is then etched to remove the unnecessary portions of the polysilicon layer. This etching is carried out by employing a Chemical Mechanical Polishing (CMP) process. The CMP process stops at the nitride layer, which covers the gate electrode and which serves as an etch stop layer. In this manner, referred to as a self-aligned contact method, a contact pad is formed.
As a result of this contact pad, the aspect ratio is reduced and the thickness of the insulating layer is decreased. Recall that the insulating layer is etched during the formation of a contact hole for an electrical connection to the contact pad.
This conventional method, however, suffers several drawbacks as explained further below. In the conventional fabricating method, the area of the upper surface of the contact pad is determined by two factors. First, the length of one edge of the upper surface of the contact pad in the direction of the word line is determined by the photoresist PR pattern for forming the contact pad. Second, the length of another edge of the upper surface face of the contact pad in the direction of the bit line is determined by the interval between the word lines. However, the alignment margin of a buried contact (BC) or a direct contact (DC) is determined by the size of the upper surface and by the size of the cell contact. For example, if the design rule of the DRAM cell is 0.15 microns, the maximum size of the pad is 0.15 micronsxc3x970.15 microns. If the minimum size of the contact is 0.1 microns, then the alignment margin of the contact relative to the pad is as small as 0.025 microns. However, the present alignment margin for etching processes is 0.05 microns or more, and accordingly, an alignment margin of 0.025 microns is not sufficient, making it difficult to fabricate the pad.
The present invention seeks to overcome one or more of the above-described drawbacks of the conventional contact pad forming technique.
Accordingly, it is an object of the present invention to provide a method of fabricating a contact pad for a semiconductor device, in which the upper surface area of the contact pad is increased, thereby achieving a sufficient alignment margin between the contact pad and a contact, which is electrically connected to the contact pad.
To achieve this and other objects, the present invention provides a method for fabricating a contact pad for a semiconductor device. The semiconductor device comprises a semiconductor substrate having at least two conductive patterns, and the conductive patterns are covered by a first insulating layer. The method according to the present invention includes: forming a second insulating layer on the semiconductor substrate, the second insulating layer having an etch selection ratio relative to the first insulating layer. The second insulating layer is anisotropically etched using a pad forming mask, to form an opening so as to expose the upper surface of the semiconductor substrate between the conductive patterns. The side walls of the opening in the second insulating layer are then isotropically etched, using the pad forming mask again, to expand the size of the opening. The expanded opening is filled with a conductive layer to form a contact pad to be electrically connected to the semiconductor substrate.